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Smart Quad Channel Low-Side Switch
TLE 5216 G
SPT-IC Features * * * * * * Overload protection Short circuit protection Cascadeable serial diagnostic interface Overvoltage protection C compatible input Electrostatic discharge (ESD) protection P-DSO-20-10
Type w TLE 5216 G w New Type Application
Ordering Code Q67006-A9206
Package P-DSO-20-10
* All kinds of resistive and inductive loads (relays, electromagnetic valves) * C compatible power switch for 12 V applications * Solenoid control switch in automotive and industrial control systems
Semiconductor Group
1
1998-06-22
TLE 5216 G
General Description Quad channel Low-Side Switch in Smart Power Technology (SPT) with four separate LOW active inputs and four open drain DMOS output stages. The TLE 5216G is protected by embedded protection functions and designed for automotive and industrial applications. Product Summary Parameter Supply voltage Drain source clamping voltage (OUT1 - OUT4) ON resistance Output current Symbol Values 6 ... 30 75 0.35 4x2 Unit V V A
VS VDS(AZ)max RON(typ) ID
Pin Configuration (top view) P-DSO-20-10
GND N.C. IN1 IN2 OUT1 VS OUT2 SEROUT CLK GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
AEP01617
GND N.C. IN4 IN3 OUT4 RESET OUT3 SERIN CS GND
Figure 1
Semiconductor Group
2
1998-06-22
TLE 5216 G
Pin Definitions and Functions Pin No. 3 4 5 6 7 8 9 1, 10, 11, 20 12 13 14 15 16 17 18 2, 19 Symbol IN1 IN2 OUT1 Function Input switch 1; active LOW; internal pull-up Input switch 2; active LOW; internal pull-up Output switch 1; overload and shorted load protected Supply voltage Output switch 2; overload and shorted load protected Data-out of serial diagnostic interface; open drain Clock for serial diagnostic interface Ground Chip select for serial diagnostic interface; internal pull-up Data-in of serial diagnostic interface; internal pull-up Output switch 3; overload and shorted load protected Reset; active LOW; shuts down all outputs and resets the error flags Output switch 4; overload and shorted load protected Input switch 3; active LOW; internal pull-up Input switch 4; active LOW; internal pull-up Not connected
VS
OUT2 SEROUT CLK GND CS SERIN OUT3 RESET OUT4 IN3 IN4 N.C.
Semiconductor Group
3
1998-06-22
TLE 5216 G
V BB
RESET
VS
GND
TLE 5216 G
V Internal
Overload Open Load IN1 Logic Channel 1 Short to GND dv/dt Circuit Current Limit Clamp Regulator OUT1
IN2 IN3 IN4 Logic, Protection- and Power-Circuit of Channel 2-4 (equivalent to Channel 1)
OUT2 OUT3 OUT4
Logic Channel 1-4 Serial Diagnostic Interface
SERIN
SEROUT
CS
CLK
AES02013
Figure 2 Block Diagram
Semiconductor Group 4 1998-06-22
TLE 5216 G
Application Description This IC is specially designed to drive inductive loads up to 2 A nominal current (valves, relays, etc.). Integrated clamp-diodes limit the output voltage when inductive loads are turned off. For the detection of errors at the load there is a serial diagnostic interface, which monitors the following errors for every output separately: - open load in inactive mode - shorted output (shorted to ground) in inactive mode - overload or shorted load in active mode Circuit Description The block diagram shows the four independent power drivers with the referring logic block and the serial diagnostic interface which stores and transfers the diagnostic signals to the external circuit. Each power switch connects a high side load to ground when a LOW signal applies at the inputs. To protect the IC against short circuit and over load each output is provided with a current limitation and a delayed overload shutdown. The slew rate of the switching process is limited internally. The integrated clamp diodes limit the voltage at the output to VDS(AZ), when inductive loads are switched off. The maximum power dissipation, which is given from the static and dynamic thermal resistance, limits the allowable inductive energy. A diode in parallel to every output clamps negative voltage. All outputs, preferably the outputs 1 and 2 and the outputs 3 and 4 may be used in parallel (no addition of max. freewheeling energy). A curve of the output voltage is shown in figure 6. The diagnostic block monitors the voltages across the power switch. If in active mode (LOW level input) there is a higher voltage than VDS(OV) for a time longer than tVDS(OV), the diagnostic block will show an overload in the error register and the affected power switch will be shut off. The switch can only be reactivated if the corresponding input is switched off and then on again. In inactive mode (HIGH level at input) open load or shorted output (shorted load to ground) is detected and signalled to the serial diagnostic interface. If the voltage across the power switch is lower than VDS(OL) for the time tVDS(OL) (min. 50 s) open load is identified. If the voltage is even lower than VDS(SH) for the time tVDS(SH) (min. 30 s) "shorted to ground" is detected. An internal voltage divider will pull the output to the voltage VDS if there is an open load. A new error on the same output stage will over-write the old error report. The protocol of the serial diagnostic interface includes independent error reports for each output driver. As soon as an error is latched into the error register the serial data output (SEROUT) of the interface will go LOW (while CS is still HIGH). If the chip select gets a LOW signal
Semiconductor Group
5
1998-06-22
TLE 5216 G
(CS = L), all error reports can be shifted out serially. The rising edge of the CS will reset all error registers. The function of the serial diagnostic interface is shown in figure 7. The data input (SERIN) allows several TLE 5216 G or other serial diagnostic interfaces to be cascaded. A LOW signal on the reset pin (RESET) or a supply voltage lower than the operating range (4.5 V) will erase the error register and disable all four power switches. Absolute Maximum Ratings Tj = - 40 C to 150 C Parameter Supply voltage Input voltages IN1 ... IN4, SERIN, CLK, CS, RESET Status output voltage Data OUT (SEROUT) Operating temperature range Storage temperature range Output current per channel Ground pin current Symbol Values - 2 ... 40 - 0.3 ... 7 - 0.3 ... 10 - 40 ... 150 - 50 ... 150 Unit V V V C C
Tj = 25 C Tj = 125 C Tj = 25 C Tj = 125 C
VS VIN VSEROUT Tj TStg ID(AZ) ID(AZ) IGND IGND
- 3.8 ... 3.8 A - 2.95 ... 2.95 A - 10 ... 10 -8...8 5 0.5 0.2 A A K/W K/W K/W
Thermal resistance (junction-case static) See diagrams P-DSO-20-10 RthJC Transient thermal impendance tp = 100 s; square pulse ZthJC tp = 100 s; triangle pulse ZthJC
Note: Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit.
Semiconductor Group
6
1998-06-22
TLE 5216 G
Operating Range Parameter Supply voltage Supply voltage outputs switchable; no diagnostic VS Input LOW voltage Input HIGH voltage Clock input HIGH voltage Inverse current at output Junction temperature Clock frequency Clock pulse width CS pulse width Setup time CS to CLK
1)
Symbol
Limit Values min. max. 30 6 4.5 - 0.3 2 2.4 - 0.3 - 40 0 400 2 2 150 500 1 6 6
Unit V V V V V A C kHz ns s s
VS
VS > 6 V VS > 6 V VS > 6 V VS > 6 V
isolated cooling fin
1)
VINL VINH VCLKH ID Tj fCLK tCLKH, tCLKL tCSH, tCSL tCSC
VS > 6 V VS > 6 V VS > 6 V VS > 6 V
If inverse current occurs at output 2 or 3, then provide external pull-up resistor 5.6 k to + 5 V at input DIN.
Note: In the operating range the functions given in the circuit description are fulfilled.
Semiconductor Group
7
1998-06-22
TLE 5216 G
Electrical Characteristics VS = 6 V to 18 V; Tj = - 40 C to 150 C (unless otherwise specified) Parameter Symbol Limit Values min. Power Supply (VS) Supply current Outputs ON IS Outputs OFF IS 3.5 8 8 15 mA mA typ. max. Unit
Power Outputs ON state resistance Tj = 25 C; ID = 2 A; all VDS > 0 V RDS(ON) Tj = 125 C; ID = 1.5 A; t > 100 s RDS(ON) Clamping voltage (OUT1 - OUT4) ID = 1 A; 0 < Tj < 125 C; all VDS > 0 V VDS(AZ) Negative clamping voltage Tj = 25 C; ID = - 0.3 A VDS(AZ) Current limitation 65 -1 3.0 2.8 2.25 3.6 3.3 2.6 0.2 0.35 0.55 70 0.4 0.63 75 V
- 0.5 V 4.2 A 3.8 A 2.95 A 0.5 mA
Tj = 0 C; VDS = VDS (OV) ID(lim) Tj = 25 C; VDS = VDS (OV) ID(lim) Tj = 125 C; VDS = VDS (OV) ID(lim)
Leakage current VS = 0 V; VDS = 12 V; all VDS > 0 V IR Digital Inputs Inputs IN1 ... IN4, CS, SERIN Input LOW current Input HIGH current Input hysteresis Input Clock (CLK) Input current Input hysteresis 0 V < VINCLK < 5 V IINCLK - 20 0.5 0 V < VIN < 2 V IINL
- 200 - 100 - 50 A - 20 0.5 0 0.6 5 A V
VIN = 5 V IINH VINHys
2 0.7
5
A V
VINCLKHys
Semiconductor Group
8
1998-06-22
TLE 5216 G
Electrical Characteristics (cont'd) VS = 6 V to 18 V; Tj = - 40 C to 150 C (unless otherwise specified) Parameter Symbol Limit Values min. Input Reset Input current Input hysteresis 0 V < VINR < 2 V IINR - 25 0.5 - 10 0.6 -5 A V typ. max. Unit
VINRHys
Input Currents in Case of Inverse Current at Output ID = - 0.3 A; VS = 0 V; 0 V < VIN < 5 V Inputs CLK, SEROUT, CS, SERIN Inputs IN1 ... IN4 Input RESET Timings Data valid SEROUT after CLK no 100 % testing tDDA Output ON delay 0 0 0 -3 - 15 10 150 1.4 2.4 -1 -8 14 400 10 10 3 -5 20 ns s s s V/s V/s
IIN IIN IIN
200 100 25
A A A
RL = 12 tDON Output OFF delay RL = 12 tDOFF Difference of delays RL = 12 tDON - tDOFF Output slew rate falling CL = 1 nF; 10 V 2 V Sf Output slew rate rising ID = 1 A; 5 V 55 V Sr
Diagnostic Output (SEROUT) Output leakage current Output LOW voltage
VSEROUT = 5 V ISEROUTH 0 V < ISEROUT < 1.6 mA VSEROUTL
0 0 0.2
5 0.5
A V
Semiconductor Group
9
1998-06-22
TLE 5216 G
Electrical Characteristics (cont'd) VS = 6 V to 18 V; Tj = - 40 C to 150 C (unless otherwise specified) Parameter Symbol Limit Values min. Diagnostic Functions Overload threshold Overload delay Open load output voltage Output ON VDS(OV) 1.5 30 3.3 6.7 5 4.3 9.3 50 2.4 4.5 30 2 80 3.8 7.7 15 4.7 10.2 130 2.8 5.4 80 2.5 200 4.3 8.7 40 5.2 11 250 3.3 6.3 200 V s V V k V V s V V s typ. max. Unit
VS = 12 V; VBB = 12 V tVDS(OV) VS = 6.5 V; outputs OFF VDS VS = 12.5 V VDS
Differential open load output resistance outputs OFF RD Open load threshold VS = 6.5 V; outputs OFF VDS(OL) VS = 12.5 V VDS(OL) Open load delay
VS = 12 V tVDS(OL)
Shorted to ground threshold VS = 6.5 V; outputs OFF VDS(SH) VS = 12.5 V VDS(SH) Shorted to ground delay
VS = 12 V tVDS(SH)
Note: The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at TA = 25 C and the given supply voltage.
Semiconductor Group
10
1998-06-22
TLE 5216 G
Test Circuits
VBB
100 F IN 1 IN 2 Load
VS
OUT1 OUT2
D1 D2 D3 D4
VS
=
+ IN 3
TLE 5216 G
OUT3 OUT4
V INH
IN 4 RESET SERIN CS
=
CLK SEROUT GND
5 k
VDS (OUT4) VDS (OUT3) VDS (OUT2) VDS (OUT1)
= 5V = V INL
+
AES01437
Figure 3 Test Circuit 1
100 F + 12 V =
IN 1 IN 2 IN 3 IN 4 RESET SERIN + 5V = CS
VS
OUT1 OUT2
12 3 mH a b 1 nF
TLE 5216 G
OUT3 OUT4
CLK SEROUT GND
AES01438
Figure 4 Test Circuit 2
Semiconductor Group 11 1998-06-22
TLE 5216 G
S
100 F IN 1 IN 2 6 ... 18 V = + IN 3 IN 4 RESET SERIN CS a b 5V = +
VS
OUT1 OUT2
12 12 12 12
TLE 5216 G
OUT3 OUT4 CLK SEROUT GND
AES01439
Figure 5 Test Circuit 3
Input
H L
VDS (OUT) t VDS (OV) VDS (AZ)
Output Voltage
VLoad Sf
50% 0 "Over Load"
Sr t VDS (OL) VDS (OL) t VDS (OL) t DOFF t VDS (SH) t VDS (SH) VDS (SH)
"Shorted"
VDS (OL)
t DON
VDS (OV)
VDS (SH) t
AED01442
VDS(AZ)
"Open Load"
Figure 6 Switching Waveforms with Inductive Loads
Semiconductor Group 12 1998-06-22
Error
Semiconductor Group
tCSL tCSC tCLKH tCSH tDSET tDHOLD
Di0 Di1 Di2 Di4 Di3 1/f CLK
No Error
H
CS
L
H
CLK
L
tCLKL t DDA
H
Figure 7 Serial Diagnostic Interface Timing Diagram
D0 D1 1 2 3 4 D2 D4 D7 D3 D5 D6 Di0 Di1 Di2 Di3 Di4 Normal Function Overload, Shorted Load Open Load Shorted to Ground No Error Overload, Shorted Load Open Load Shorted Load to Ground HH HL LH LL
AED01445
13
SERIN
L
H
SEROUT
L
tV
Power Output Assignment
H
Error Code:
L
TLE 5216 G
1998-06-22
TLE 5216 G
Thermal Resistance for P-DSO-20-10
10 1 K/W
AED01893
Z th
10 0 5 1 Switch 2 Switches 4 Switches
10 -1 5
10 -2 10 -2
5
10 -1
5
10 0
5 10 1 Pulse width (square)
ms
10 2
Note: Thermal resistance is measured at TC = 25 C and Tjpeak = 45 C. Multiple switches are equally loaded at the same time.
Tj1 0.4 K/W 0.2 mJ/K Tj2 0.4 K/W 0.2 mJ/K Tj3 0.4 K/W 0.2 mJ/K Tj4 0.4 K/W 0.2 mJ/K 0.8 K/W 0.6 mJ/K 0.8 K/W 0.6 mJ/K 0.8 K/W 0.6 mJ/K 0.8 K/W 0.6 mJ/K 0.8 mJ/K 0.8 mJ/K 0.8 mJ/K 0.8 mJ/K 1.4 K/W 2 mJ/K 1 K/W 1.4 K/W 2 mJ/K 1.4 K/W 2 mJ/K 1 K/W 1.4 K/W 2 mJ/K 2.4 K/W 100 mJ/K 0.75 K/W 2.4 K/W 2.4 K/W
PV1 (W)
PV2 (W)
15 K/W
15 K/W 2.4 K/W
PV3 (W)
PV4 (W)
TC (K)
AES01895
Figure 8 Thermal Equivalent Circuit for P-DSO-20-10 Note: Thermal equivalent circuit is valid at TC = 25 C and 25 C < Tj < 45 C. At TC = 110 C and 110 C < Tj < 130 C, Zth is 15 % higher. For high power transients with Tj max - TC 100 K add 25 % headroom for thermal non-uniformity.
Semiconductor Group 14 1998-06-22
TLE 5216 G
Definition of Dynamic Thermal Resistance (triangle Pulse)
P Z th = ( T j max - T j 0 ) /Pmax Pmax
Maximum Freewheeling Energy for Inductive Loads
100 mJ
Freewheeling Energy
AED01447
80 70 60 50 40 30
f= 10 Hz
50 Hz
0
Tj
0
100 s t
100 Hz
f= 10 Hz 50 Hz
100 Hz
TC =60 C
T j max
20 10
Tj 0
0
TC =110 C
0.5 1.0 1.5 2.0 A 2.5
100 s t
AED01446
0 0.0
Switching Current
Maximum Freewheeling Energy for Inductive Loads with Various Switches in Parallel TC = 110 C, f = 10 Hz
40 mJ
Max. Freewheeling Energy
AED01448
30 3...4 Switches
20
2 Switches 10 1 Switch
0
0
2
4
6
8 Switching Current
A
10
Semiconductor Group
15
1998-06-22
TLE 5216 G
Diagnostic Threshold versus Supply Voltage
VDS VS
Current Limitation versus Temperature
D(lim)
5 A 4
AED01444
Normal Function
VDS (OL) VDS
Error: Open Load Open Load Output Voltage
3
max
min 2
VDS (SH)
Error: Shorted to Ground
1
6
12
V
18
VS
AED01443
0 -40
0
50
100
C 150
Tj
VS
*)
4
A9-13 Control 2.IC A8 Diagnosis Chip select A7 Diagnosis Clock A6 Power On Reset
VS
RESET CLK
VS
RESET CLK
VCC
5.6 k
VCC
5.6 k
VCC
3.3 k A5 1-4 4 A1-4
Microcontroller i.e. SAB 80515
TLE 5216 G CS
SERIN SEROUT IN 1-4
TLE 5216 G CS
SERIN SEROUT IN
Diagnosis Data In Control 1.IC
To Loads
1-4
OUT
GND
To Loads
1-4
OUT
GND
*) The capacitance depends on the inductance and current load of the supply.
AES01449
Figure 9 Application Circuit
Semiconductor Group 16 1998-06-22
TLE 5216 G
Package Outlines P-DSO-20-10 (Plastic Dual Small Outline Package)
3.5 max.
1.2 -0.3
0 +0.15 3.25 0.1
1.3
0.25 +0.0 7 -
0.02
11 0.15 1) 2.8
B
15.74 0.1 1.27 0.4
+0.13
0.1 0.25
M
6.3 14.2 0.3
A 20x
Heatsink 0.95 0.15 0.25
M
20
11
Index Marking
1 1 x 45
10
A 1) Does not include plastic or metal protrusion of 0.15 max. per side
15.9 0.15 1)
GPS05791
5 3
B
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Semiconductor Group 17
Dimensions in mm 1998-06-22
GPS05791

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